Logic track circuit

ABSTRACT

A binary logic circuit responsive to three binary logic input signals produced by respective railway signalling circuit means coupled to a section of track and located at a train highway crossing and track portion on either side thereof for activating a warning system or crossing gate when a train is approaching or traversing a crossing from either direction and thereafter deactivating the system in a fail safe manner. The logic circuit includes a plurality of interconnected AND, OR, AND NOT logic gates. Additionally, a pair of flip-flop circuits are also connected into the circuitry for providing a determination of whether the train is approaching or receding from the crossing. The logic combination of the input signals also checks the condition of the circuit itself and provides an output indicative thereof to the system whenever the circuit adopts an abnormal state of operation.

United States Patent Pal [451 Sept. 12, 1972 [54] LOGIC TRACK CIRCUIT[72] Inventor: Ajoy Kumar Pal, 2035 Prentiss Drive, Apt. 210, DownersGrove, 111. 60515 [22] Filed: May 7,1971

21 Appl. No.: 141,269

[52] US. Cl ..246/125, 246/40 [51] Int. Cl. ..B61l 1/02 [58] Field ofSearch ..246/34 CT, 40, 125-l30, 246/249, 34 R [56] References CitedUNITED STATES PATENTS 3,333,096 7/ 1967 Ohman et a1. ..246/34 CT FOREIGNPATENTS OR APPLICATIONS 915,701 7/1954 Germany ..246/34 R PrimaryExaminer-Gerald M. Forlenza Assistant Examiner-George H. LibmanAttrney-Emory L. Groff and Emory L. Groff, Jr.

[5 7] ABSTRACT A binary logic circuit responsive to three binary logicinput signals produced by respective railway signalling circuit meanscoupled to a section of track and located at a train highway crossingand track portion on either side thereof for activating a warning systemor crossing gate when a train is approaching or traversing a crossingfrom either direction and thereafter deactivating the system in a failsafe manner. The logic circuit includes aplurality of inter connectedAND, OR, AND NOT logic gates. Additionally, a pair of flip-flop circuitsare also connected into the circuitry for providing a determination ofwhether the train is approaching or receding from the crossing. Thelogic combination of the input signals also checks the condition of thecircuit itself and provides an output indicative thereof to the systemwhenever the circuit adopts an abnormal state of operation.

14 Claims, 3 Drawing Figures f 14 s 1 l2 V.

3 L02 tug 22 Y I INPUT CROSSIG. OUTPUT CPL'G RELAY CPL'G AMA 29 H|Z 2o I32 X \(IQ FILTER l Mb osc.

PATENTED SEP 12 I972- SHEET 2 [IF 2 Tll'l nnn |I||| IIIIH INVENTOR.

WILLARD L. GE/GER LOGIC TRACK CIRCUIT BACKGROUND OF THE INVENTION 1.Field of the Invention This invention relates to highway crossingprotection systems for railroads and more particularly to binary digitallogic circuitry which will provide fail safe operation of warning signalapparatus or crossing gates.

2. Description of the Prior Art All the presently known overlay trackcircuits for highway crossing protection for railway apparatus use audiofrequency transmitters and receivers in various configurations witheither the transmitter at the end of the warning zone and the receiverat the crossing or with the receiver at the end of the warning zone andthe transmitter at the crossing. The basic principle involved in all ofthese track circuits is the same, however, in that an audio frequencycurrent is transmitted into the rails by the transmitter which isadapted to energize electromechanical track relays incorporated withinthe receivers. Whenever a locomotive or other rolling stock shunts thetransmitted current, the relay or relays become deenergized. Otherelectromechanical relays known as stick relays are also incorporatedwithin the receiver and are used to differentiate between trainsapproaching to or receding from the crossing. The combination of stickand track relays determine the conditions of track, whether occupied ornot, and provide signals accordingly to a relay which controls thecrossing gate. The major disadvantage in this technique lies in the useof approximately 8,000 to 10,000 feet of cable wire and cableingnecessary either to energize the transmitter at the end of the warningzone or to bring the receiver signal to the Crossing from the end of thewarning zone. The transmitter and receiver in their presentconfigurations also present problems in maintenance when eithermalfunctions.

Moreover, electromechanical relays incorporated within the receiver needperiodic maintenance in order to guarantee reliable operation. With theuse of such relays, it is difficult to limit the effective length ofthis track circuit, inasmuch as the effective or electrical length asdetermined by the electrical track resistance referred to as the trackballast resistance will vary with a change in climatic condition. Theserelays are likely to operate improperly whenever the resistance of thetrack ballast changes unless special care has been paid to the amount ofcurrent flowing through the rails. In some cases, theseelectromechanical devices are replaced by highly sensitivetransistorized devices or ferrite cores but there is no technique, knownat present, which can place both the transmitter and receiver at thecrossing without the use of cableing.

SUMMARY In view of the above, it is the object of this invention toprovide an improved railway signalling system for warning a motorist ata railway crossing and/or indicating occupancy of a portion of track bya train. The subject invention briefly comprises, inter alia, a constantcurrent audio frequency transmitter of AC signal coupled across therails of a section of track intermediate the location of a pair ofseparated narrow band AC shunt circuits respectively coupled across thetracks. The transmitter is located, for example, at a highway crossinglocated midway between the shunts so that the track section is dividedinto a first and a second track portion on opposite sides of thecrossing. A resonantly tuned transformer is coupled by means of itsprimary circuit across the track proximately to or at the location ofthe transmitter. The voltage across its secondary circuit is rectifiedand fed to a first threshold circuit which is adapted to provide a firstbinary logic signal output. A pair of current" transformers are coupledto the track on either side of the crossing adjacently thereto asopposed to near the location of the shunts. The respective secondarywindings of the current transformers are coupled to rectifiers andrespective threshold circuits which provide a second and third binarylogic output signal therefrom. The constant current transmitter thustransmits current into three current paths which include the tunedtransformer connected to the track at thecrossing as well as the currentflowing in the two track portions containing the current transformersand the respective shunts. As a train approaches or recedes from thecrossing the amount of current flowing in the first and second trackportion as well as the tuned transformer will change as the wheels ofthe train short out more or less rail segments of the track portions.The three binary logic signals are utilized to provide an indication ofthe occupancy condition of the track between the two shunts. A binarylogic circuit comprised of AND, OR, and NOT logic gates is coupled tothe three threshold circuits. It is responsive to the three binaryoutput signals therefrom and performs a predetermined logic functiontaking into account all possible conditions to operate circuit meansindicative of either the approach of a train from either direction, thepresence of the train at the crossing, the clearance of the track uponthe passing of a train, as well as providing a self check of its ownlogic output.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an electrical block diagramillustrative of a first embodiment of the subject invention;

FIG. 2 is a diagram illustrative of waveforms of the outputs of thethree transformers utilized by the subject invention; and

FIG. 3 is an electrical block diagram of a second embodiment.

DESCRIPTION OF THE PREFERRED EMBODIMENT Referring now to the drawingsand more particularly to FIG. 1, reference numerals 10 and 12 designatetwo rails of a railroad track across which are connected two seriesresonant circuits 14 and 16. Each is comprised of an inductance and acapacitance and is commonly referred to in the art as AC shunts. Theshunts 14 and 16 are shown disposed on opposite sides of a highwaycrossing 18 shown located preferably midway therebetween. An AC source20 comprising a constant current, audio frequency transmitter is coupledacross the rails 10 and 12 at the crossing 18 at the connections 21 and22. The connections 21 and 22 are substantially opposite each other sothat as a train rolls over the location of the connections, the source20 will be shorted out by the wheels and axle of the train.

A first transformer 24 tuned by means of the capacitor 26 and theinductance of the primary winding 28 is also coupled across the rails 10and 12 at the crossing adjacent the connections 21 and 22. The primarycircuit of the transformer 24 is tuned to the frequency of the AC source20 so as to allow only current transmitted to the rails 10 and 12 at thecrossing to pass through it. The secondary winding 30 of the transformer24 is coupled to a full-wave bridge rectifier 32 which provides a DCoutput which is coupled to a first threshold circuit 34 which may be,for example, a Schmitt trigger circuit. The threshold circuit 34 isoperatively biased by means not shown to provide an output whenever theprimary winding 28 of the transformer 24 is energized by the AC source20, but does not provide an output when the primary winding becomesdeenergized whereupon the secondary current drops to zero. The thresholdcircuit 34 is said to change from a binary I state to a binary state.

A second and third transformer 38 and 36 are coupled by means of theirrespective primary windings 40 and 42 to the rail on opposite sides ofthe crossing 18 in relatively close proximity thereto, as opposed to theposition of the shunts 14 and 16. The primary windings 40 and 42comprise parallel branches of, for example, a single turn of copper wirewhich will offer less resistance and inductive reactance to audiofrequency current than the rail itself. Additionally the primarywindings 40 and 42 are respectively connected across the track joints 41and 43. The joint may be of the insulated or regular type; however, ifit is an insu lated type, there also includes means, not shown, whichprovides for electrical continuity for any other track currents. Thetransformers 36 and 38 are referred to as current transformers becausethe voltage appearing across the secondary windings 44 and 46 islinearly proportional to the current flow in the primary windings 40 and42, respectively. The secondary winding 46 is coupled to a secondfull-wave bridge rectifier 48 by means of a series L-C filter 51. Thefilter 51 is tuned to the frequency of the constant current source 20 sothat the bridge rectifier 48 only receives AC signals transmitted fromthe audio frequency source 20. The output of the bridge rectifier 48 isconnected to a second threshold circuit 50. In a like manner thesecondary winding 44 of the transformer 36 is connected to a thirdfull-wave rectifier bridge 52 by means of a tuned series filter 54. Alsothe output of the bridge rectifier 52 is connected to a third thresholdcircuit 56. The threshold circuits 50 and 56 are identical with respectto the threshold circuit 34. The threshold circuits 50 and 56 moreoverchange from a binary 0 state to a binary I state whenever the currentsthrough the respective primary circuits increase from a predeterminedvalue indicative of a no train condition in the respective track portionon either side of the crossing 18 due to the passage of a train over thetrack between the shunts l4 and 16.

In the subject embodiment considered thus far, the AC source 20transmits a substantially constant current, sinusoidal audio frequencysignal into the rails at the connections 21 and 22 and current flowsthrough the rails 10 and 12 in two track portion loops including theshunts 14 and 16 respectively with the transformers 36 and 38 providingoutputs across their respective secondary windings 44 and 46proportional to the magnitude of the loop currents. Additionally, aportion of the constant current output is divided into the primarywinding 28 of the tuned transformer 24 located at the crossing. Themovement of a train in either direction over the section of trackintermediate the shunts l4 and 16 affects the voltage output of thetransformers 36 and 38 due to the shorting effect of the train wheels asthe train moves across the rails 10 and 12. For example, as a trainmoves from left to right toward the crossing 18 shown in FIG. 1 thetrain, not shown, first passes the shunt 16 and in doing so reduces thetrack resistance in track portion-1 which will cause an increase in therespective loop current. Since a constant magnitude of current iscoupled to the track, the current to the transformer 24 will be reducedin substantially like amount. The track portion '2, including the shuntportion 14 and transformer 36, however, is relatively unaffected. Thusin a no train condition, the current flowing through each of the threecircuit branches is proportional to its own impedance; however, thetrain movement over the rails 10 and 12 will affect the circuitimpedance of the track portions on either side of the crossing. Sincethe threshold circuits 34, 50 and 56 provide outputs of a binary nature,i.e., having two possible output states, the signals A, B and Cgenerated by the threshold circuits 50, 34 and 56 shown in FIG. 1,respectively comprise logic input signals, the combination of which areadapted to provide an indication of all possible conditions of the tracksection on either side of the crossing 18.

The following truth table I-A illustrates the track condition andrequired operating state of for example, a crossing gate located at arailroad crossing for trains moving from track portion-1 toward trackportion-2.

gate open Considering now the case for trains moving from trackportion-2 toward track portion-l reference is made to the truth tableII-A shown below.

TRUTH TABLE II-A A B C condition of track & crossing gate state 0 1 0No-traln-gate open 0 l 1 Train approaching-gate closed 0 0 0 Train onthe crossing-gate closed I l 0 Train receding-gate open 0 0 1 NotPossible state I 1 1 Not Possible state I 0 0 Not Possible state 1 0 INot Possible state 0 I 0 No-train-train clear of track portion-1.

Gate open.

In order to make the system fail safe, the NOT POSSIBLE states shown inthe Truth Tables l-A and lI-A must be considered and the crossing gatemust be activated whenever a NOT POSSIBLE situation develops within thecircuitry for logically implementing the truth tables. This will beconsidered subsequently. It is also evident from the above that thecombination of the signals A, B and C are the same when a trainapproaches the crossing 18 from track portion-1 as a train receding fromthe same crossing in the opposite direction. In order to differentiatesuch a situation, a direction sense can be obtained by the use of twoadditional signals x and y, such as shown by the partial Truth TablesI-B and II-B illustrated below.

TRUTH TABLE I-B A B C x y Condition of gate It is evident that thebinary states of x and y for the two middle conditions of the truthtables merely reverse states. These signals can be generated whenever achange of state of the threshold circuits 50 or 56 changes state due tothe increased flow of current through the rails caused by a trainapproaching toward the crossing. Each will differentiate between trainsreceding from a crossing and trains approaching the crossing until thetrain has passed out of the track portions 1 and 2.

In view of the truth tables illustrated above, a signal having forexample a binary 1 state which is indicative of a track conditionnecessitating the actuation of a warning device or closing at crossinggates must satisfy the following Boolean equation:

K-E-C A-R'C A-fi-C A-B-C +K-+K-B-0x A-BQ- y 1 l. Equation (1) can besimplified by rearranging terms to:

An embodiment of a logic circuit adapted to mechanize or implementequation (2) is additionally shown in FIG. 1 and constitutes a pluralityof interconnected AND, OR, and NOT binary logic gates as well as a pairof bistable circuits commonly referred to as flip-flops. The twoflip-flop circuits are utilized for deriving the Yand ysignals referredto above.

More particularly, the binary logic signal A from threshold circuit 50is commonly fed to a first NOT circuit (logic inverter) 58 as well as toone input of a four input OR gate 60 and the AND gates 62 and 64 whichhave two and three inputs respectively. The B binary logic signal is fedfrom threshold circuit 34 to the input of the NOT circuit 66 as well asto one input of the three input AND gate 68. The third binary logicsignal C generated by the threshold circuit 56 is coupled to the inputof the NOT circuit 70 as well as to one input of the four input ORcircuit 72 and one input of the two input AND gate 62 and 74.

The complementary binary logic signal A provided at the output of theNOT circuit 58 is coupled into one input of the three input AND gates 68and 76 as well as to one input of the OR circuit 72. The complementarysignal 8 provided at the output of the NOT circuit 66 is coupled to oneinput of the OR circuits 60 and 72 as well as to one input of the ANDgates 64, 74 and 76. Similarly, the complementary logic signal Cgenerated by the NOT circuit 70 is commonly coupled to one input of theOR circuit 60 as well as one input of the AND gates 68, 64, and 76. Theoutpu t of the AND circuit 68 comprises the logic signal A-B'C. Thissignal is commonly applied to the R(reset) inputs of the flip-flops 78and 80 through a differentiator and a diode D The outputs of the ORgates 60 and 72 which comprises the logic signals A++C+ and A+ B+C+:v,respectively, are each fed to a separate input of the two input ANDgates 82 which is followed by a NOT gate 84 coupled thereto.Additionally, the logic output signal-of the OR gate 60 is fed to theS(set) input of the flip-flop circuit through a differentiator 79 and adiode D while the output of the OR gate 72 is fed to the corresponding Sinput of the flip-flop circuit 78 through a differentiator 77 and adiode D The output of the AND gates 76, 62, 74, and 64 are applied toseparate inputs of a four input OR gate 86 whose output comprises thelogic signal A-C+B-C A--C +A'E-C. The output of the NOT circuit 84 onthe other hand comprises the logic signal (A+E+C+E) X+I+c+y With theoutputs of the OR circuit 86 and the NOT circuit 84 applied to separateinputs of a two input OR gate 88, the output therefrom comprises abinary logic signal corresponding to the equation (2).

Normally when there is no train on the track portions 1 and 2 shown inFIG. 1, the primary windings 40 and 42 of the current transformers 36and 38, respectively, will be energized with a certain amount of thecurrent injected to the rails 10 and 12 at the connections 21 and 22located at the crossing 18. As noted earlier, the amount of current willdepend on the impedance of the two track portions as well as theimpedance of the tuned primary circuit of transformer 24 also coupled tothe rails 10 and 12 at the crossing 18. The current flowing through therespective secondary windings 30, 44 and 46 will depend on the turnsratio of each of the transformers according to the relationship:

Current through secondary winding Current through primary windingPrimary number of turns 7 igecondary number of turns The values of theimpedancesoftlie track 655115 1" and 2 as well as the impedance of thetuned circuit are so selected in combination with the turns in therespective transformers so that the currents flowing through the inputsof the threshold devices 50, 34, and 56 at no train condition will causethreshold circuit 50 to provide a binary 0 output, threshold circuit 34to provide a binary l output, and threshold circuit 56 to provide abinary output. The combination of the binary logic outputs A, B, and Cat this time can be expressed as (0, l, 0). This combination of binarysignals applied to the inputs of the AND gate 68 will provide a binary lat the output thereof which is commonly fed to the differentiator 75.Whenever this output changes from a binary 1 to a binary 0 or from abinary "O" to a binary l there is an output across the differentiator75. The signals at the R- terminal of the flipflops appear only at theoutput terminal A from binary 0 to binary l however. This resets theflip-flops causing a binary 0 to appear at the output terminal A thereofand comprises outputs Y and 3 from the flipflops 78 and 80. Whenever theoutputs of the OR gates 60 or 72 change from a binary l to a binary O,the respective differentiator and diode combination will provide asignal to set the respective flip-flop, causing a binary l to appear atthe A terminal of the respective flip-flop. This state will persistuntil the combination (A, B, C) turns back to (0, 1, 0) at which timeboth flipflops 78 and 80 will be reset.

At the time when the signal (A, B, C) is a binary (0, l, 0) there willbe a binary 1 provided at the output of the AND gate 82; however, abinary 0 will appear at the output of the NOT circuit 82. In a similarmanner, a binary 0 will appear at the outputs of the AND gates 76, 62,74 and 64. A binary 0 output will likewise be presented at the output ofthe OR gate 86. Since both inputs to the OR gate 88 is a binary 0, itsoutput will be a binary 0. For such a condition of the binary output ofthe OR gate 88, no actuating signal will be coupled to externalapparatus such as a crossing relay, which will close a crossing gate orother signalling means.

When a train enters track portion-l from the left and passes the point90 on rail 10 shown in FIG. 1 located near the narrow band shunt 16, acurrent. through the track portion'l will increase as shown by waveform92 of FIG. 2 starting at the time t whereas the currents through theprimary winding 28 of transformer 24 and track portion-2 as shown bywaveforms 94 and 96, respectively, of FIG. 2 will decrease. The increaseof current through track portion-l after the time t will cause anincrease of current through a secondary winding 46 of transformer 38which will cause the threshold circuit 50 to switch states whereupon thelogic signal A will change from a binary 0 to a binary I. However, therewill be no change in states of threshold circuits 34 and 56 andconsequently the logic signals B and C will maintain its respectivebinary l and 0 state. The current through the secondary winding 46 willincrease linearly until the train reaches point 98 on rail 10. As longas the train is between points 90 and 98, the combination of the signalsA, B, C will be (1, l, 0). This will cause the output of the OR gate 72to be in a binary 0 state. This change in the output of OR gate 72 willset the flip-flop 78 whereupon the it signal will switch from a binary 0to a 1. This state of flipflop 78 will be maintained until the output ofAND gate 68 changes from binary 0 to a binary 1." Whenever any input toAND gate 82 becomes a binary 0, the output thereof will be a binary 0,resulting in a binary 1 input being provided to the OR gate 88 from theNOT gate 84. There will also be no change in the outputs from AND gates76, 62, 74 and 64, however, the output of the OR gate 88 will be abinary l which is of proper polarity to actuate a crossing relay, etc.

When the train reaches point 98, the wheels of the train next will shuntthe primary winding 42 and the current in the secondary winding 46 willimmediately drop to zero as shown in FIG. 2 at the time t The current inthe primary winding 28 will increase momentarily due to the constantcurrent input to the rails until point 100 is reached at the time t asshown in FIG. 2 whereupon the wheels and axle combination of the leadingtruck of the train will shunt connections 20 and 22 shown in FIG. 1. Thecurrent in the secondary windings 30 and 44 will also drop to zero asshown by waveforms 94 and 96 in FIG. 2. The time period between t, andt;, is of a negligible nature due to the relative proximity of points 98and 100, as well as the speed of the train. As a result the momentaryincrease in the primary current in winding 28 of transformer 24 is of atransient nature, and will not affect the operation of the crossingrelay or other signalling devices connected to the OR gate 88. Thesechanges are not abrupt due to the presence of inductance in the circuit.At the time the binary state of the signals A, B and C will become (0,0, O). This will cause a binary 1 to appear at the output of the ANDgate 82 but a binary 0 at the output of the NOT gate 84; however, abinary l will appear at the output of AND gate 76 which will effeet abinary 1 output of the OR gate 88 to render the external apparatuscoupled thereto in an operative state. The other AND gates 62, 64 and 74will have binary 0 outputs at this time.

When the last or rear wheels and axle of a train passes point 102 shownin FIG. 1 as the train passes from left to right and at a time t, asshown in FIG. 2, the three transformers 24, 36 and 38 will again becomeenergized from the constant current source 20. However, the current inthe secondary winding 44 of transformer 36 will immediately jump to ahigh value as shown by waveform 96 of FIG. 2 but the transformers 24 and38 will be energized by current less than the value of the no traincondition as shown by waveforms 94 and 92, respectively. As a result,the combination of the logic signals A, B, and C will become (0, l, 1).Under this condition the output of OR gate 72 will become a binary lwhereas the output of OR gate 60 remains a binary I because the signal Iapplied thereto has been triggered to a binary 1 state. This will bringa change in the binary output of AND gate 82 from a binary 0 state to abinary 1 Consequently, the output of NOT gate 84 will become a binary 0.This condition will be maintained until the train passes point 104 alongrail 10 near the shunt l4 whereupon the current in the transformer 36decreases to a no train value as shown at the time in FIG. 2. As aresult thereof the state of signals A, B, and C will again be (0, 1, 0).This binary combination will provide a binary 1 output from the AND gate68 which will reset the flip-flops 72 and 78 to a binary 0 againbringing the circuit to a quiescent state. For trains moving from rightto left between the shunts 14 and 16, the opposite reasoning willprevail but the operation again is the same, except that the conditionof the flip-flops 78 and will reverse as indicated in Truth Tables [-Band II- B.

Thus the combination of the differentiators 75, 77 and 79 and therespective diodes D D and D causes each flip-flop 78 and 80 to changestate only when the output pulse at the logic OR gates 60 or 72 changesfrom a binary l to a binary 0. The combination will enable pulses foryto be in a binary l state so long as a train is within the warningzone. Each flip-flop will return to its normal state (3: 0, y when theAND gate 68 turns back to a binary l from a binary 50.77

All of the logic circuitry including the threshold circuits shown inFIG. 1 are particularly adapted to be fabricated from semiconductordevices which may or may not be in integrated circuit form. However, theuse of cableing of extensive length is eliminated because thetransmitter and receiver means are located at or substantially near thecrossing. Even though current through the narrow band shunts will changedue to the variation of track resistance caused by the variation ofclimatic conditions, the current through the current transformers willremain substantially constant. As a result, the circuitry shown in FIG.1 will be more reliable than other known track circuits which performthe same function.

A second embodiment of the subject invention is shown in FIG. 3 and issimilar to the first embodiment shown in FIG. 1; however two additionaltransformers 106 and 108, referred to as summing transformers, arerespectively coupled to the full-wave bridge rectifiers 48 and 55 fromthe current transformers 36' and 38' The current transformers 36 and 38'are modifications of the current transformers shown in FIG. 1 in thatthe subject transformers now include the center tapped secondarywindings 45 and 47, respectively. Secondary winding 45 includes two endterminals 110 and 112 and a center tap tenninal 114. Similarly secondarywinding 47 includes end terminals 116 and 118 and center tap terminal120. r The secondary windings 45 and 47, moreover, are coupled togetherwith such a polarity that the current from one current transformer willoppose the current from the other. More particularly, the end terminals110 and 112 of winding 45 are directly connected to the center tapterminal 120 of winding 47 while the end terminals 116 and 118 aredirectly connected to the center tap terminal 1 14 of winding 45.Additionally the primary winding 122 of the summing transformer 106 iscoupled across the common connection between terminals 118 and 114, and120 and 112. The primary winding 124 of summing transformer 108, on theother hand, is coupled across the common connection between terminals112 and 120, and 114 and 116.

With such a connection and assuming a no train condition, irrespectiveof weather (dry or wet), the currents flowing through the track portions1 and 2 are the same due to circuit symmetry and as a result the overallor resultant currents in each primary winding 122 and 124 is zero.During this time each of the threshold circuits 50 and 56 will be in abinary 0" state. Whenever there is an unbalance of the currents flowingthrough the primary windings 122 and 124, the respective secondarywinding 126 and 128 will be energized accordingly. The thresholdcircuits 50 and 56 are biased such that they will change to a binary 1state for trains approaching from track portion 1 and from track portion2 respectively.

With the configuration shown in FIG. 3 the logic expressed in equation(2) can also be simplified to:

This eliminates the AND gates 64, 74, and 76 heretofore required andillustrated in FIG. 1.

Itshould also be pointed out with regard to FIG. 3 that in dry weatherthe ballast leakage resistances will be high whereas at wet weather theballast leakage resistances will be low. The variation of ballastleakage resistances will cause a variation of current through thecurrent transformers 36 and 38 even at no-train condition. Despite theabove fact an equal amount of current will flow through the currenttransformers. This will cause an equal but opposite ampere-turn in eachprimary winding 122 and 124 of the summing transformers 106 and 108resulting in zero outputs at the respective secondary windings 126 and128. The output pulses from the threshold circuits 50, 34, and 56 willbe a logic (0, l, 0) irrespective of the condition of ballast. Thecrossing gate will therefore remain open even without any specialattention to the amount of current flowing through the rails at varyingballast conditions.

The disconnection or breakage of connector or bonded wire will introducea high resistance in the track circuit. This additional resistance willcause in the other track portion an increase flow of current which willenergize the respective primary winding of the summation transformers106 and 108. As a result either one of the threshold devices 50 or 56will change to a binary l state from a binary 0 state. The outputs ofthe threshold circuits 50, 34 and 56 will be the same as though a trainis approaching. This will result in the operation of the crossing relay.The crossing relay will remain in this condition until the brokenconnector or wire is replaced and the track circuit is brought to normalcondition. When a train approaches the crossing point the current in thecurrent transformer 36 or 38' nearer to the approaching train willgradually increase. The primary winding of the respective summationtransformer 108 or 106 will be energized and the respective thresholddevice will change state bringing in the operation of the crossingrelay.

Thus the input connections for the summation transformers are such thatboth these transformers will remain deenergized at no train condition aswell as at varying ballast conditions because equal amount of currentwill flow through the two portions of rails. A slight unbalance ofcurrents in the two current transformers will energize the respectivesummation transformer. The respective threshold device in turn will givean output resulting in the operation of the crossing relay.

Having disclosed what is at present considered to be the preferredembodiment of the subject invention, 1 claim as my invention:

1. A system for controlling railway signalling apparatus of the typedescribed, comprising in combination:

a section of track including a pair of rails adapted to carry electricalcurrent;

a first and a second alternating current shunt coupled across said railsrespectively at opposite ends of said track section;

an alternating current source coupled across said rails at alocation-intermediate said shunts;

a first transformer having a primary and a secondary circuit includingcircuit means for coupling the primary circuit thereof across said railsadjacent the location of coupling of said alternating current source;

a second and a third transformer each having a primary and a secondarycircuit and including circuit means coupling the primary circuit inparallel circuit relationship respectively with a segment of a rail onopposite sides of the location of the coupling of said current sourceand said primary circuit of said first transformer, said current sourcefeeding a predetermined magnitude of current in diverse directionsthrough to said rails, said shunts and the primary circuits of saidsecond and third transformer as well as the primary circuit of saidfirst transformer whereupon the travel of a train over said tracksection alters the amount of current flowing in the respective primarycircuits of said three transformers by the shunting action of the wheelsthereof;

current rectifier means coupled to the secondary circuits of said first,second, third transformer for providing a DC output signal proportionalto the current flow in the respective primary circuits;

first threshold circuit coupled to said rectifier means coupled to saidsecondary circuit of said first transformer means providing an outputsignal corresponding to a first of two possible binary logic statesduring a first track condition and a second binary logic state when thecurrent in the respective primary decreases to predetermined value inresponse to a second track condition;

a second and third threshold circuit respectively coupled to the saidrectifier means coupled to the secondary circuits of said second andthird transformer, each of said threshold circuits providing an outputsignal corresponding to a mutually opposite or second binary logic stateduring said first track condition and a first binary state when thecurrent in the respective secondary circuit exceeds a predeterminedvalue in response to said second track condition; and

binary logic circuit means coupled to said first, second and thirdthreshold circuits and being responsive to the binary logic states ofthe output signals thereof to energize apparatus for a predeterminedbinary logic combination of output signals from said threshold circuits.

2. The invention as defined by claim 1 wherein said alternating currentsource comprises a constant current, audio frequency transmitter.

3. The invention as defined by claim 2 wherein said first and secondshunt circuits are resonant at the frequency of operation of saidtransmitter thereby providing a relatively low impedance to current flowbetween said rails at the location thereof, and additionally includingcircuit means coupled to the primary circuit of said first transformerfor tuning s'aid primary circuit to said predetermined frequency of saidtransmitter means so as to be responsive only to a current of saidpredetermined frequency.

4. The invention as defined by claim 3 and additionally includingcircuit means coupled to the secondary circuits of said second and thirdtransformer for providing a low circuit impedance for a secondarycurrent flow of said predetermined frequency while providing arelatively high impedance for all other frequencies.

5. The invention as defined by claim 4 wherein said second and thirdtransformers comprise current transformers wherein the current flowingin said secondary circuits is proportional to the current in saidprimary circuit and wherein said primary circuits respectively provide arelatively smaller impedance to current flow than said rail.

6. The invention as defined by claim 1 wherein said secondary circuit ofsaid second and third transformer each includes a secondary windinghaving a first and a second secondary winding portion; and

additionally including a first and second summing transformer, eachhaving a primary winding and a secondary winding; and

including circuit means coupling said first secondary winding portion ofsaid second and third transformer in mutually opposite polarityrelationship across said primary winding of said first summingtransformer and said second secondary winding portion of said second andthird transformer in mutually opposite polarity relationship across saidprimary winding of said second summing transformer; and

circuit means coupling said secondary winding of said first summingtransformer to said rectifier means coupled to said second transformerand means coupling said secondary winding of said second summingtransformer to said rectifier means coupled to said third transformer.

7. The invention as defined by claim 6 wherein said second and thirdtransformers are comprised of current transformers wherein the currentflowing in said respective secondary windings is proportional to thecurrent in said primary circuit.

8. The invention as defined by claim 1 wherein said logic circuit meansincludes means for implementing the binary logic expression:

wherein A is the binary logic output signal from said second thresholdcircuit, B is the binary logic output signal from said first thresholdcircuit, C is the binary output logic signal from said third thresholdcircuit and wherein a? and Tare binary logic signals derived by saidlogic circuit to differentiate the direction of travel of a train oversaid track section, and including a first, second and a third logicinverter circuit coupled to said first, second and third thresholdcircuit for respectively providing an output signal comprising the logicsignals A, E, and C.

9. The invention as defined by claim 8 and additionally including afirst AND binary logic circuit 76 coupled to the output of said first,second and third logic inverter 58, 66 and 70 for providing a logicoutput signal A-B'C;

a second AND binary logic circuit 62 coupled to said first thresholdcircuit 34 and said third threshold circuit 56 for providing a logicoutput signal A-C;

a third AND binary logic circuit 74 coupled to said third thresholdcircuit 56 and said second logic inverter circuit 66 for providing alogic output signal B'C;

a fourth AND binary logic circuit 64 coupled to said first thresholdcircuit 34 and said second and third logic inverter circuits 66 and 70for providing a logic output signal A-B-C;

a first OR binary logic circuit 86 coupled to the outputs of said first,second and third and fourth AND circuits 76, 62, 74 and 64, a second ORcircuit 88 having one input thereof coupled to the output of said firstOR circuit 86;

a fifth AND binary logic circuit 68 having a plurality of inputsrespectively coupled to said first logic inverter 58, said secondthreshold circuit 50 and said third logic inverter 70 for providing alogic output signal A-B-C;

a first and a second flip-flop circuit 78 and 80 having one inputterminal R coupled to the output of said fifth logic AND gate 68 andrespectively providing output signals corresponding to a? and y,-

a third OR binary logic circuit 60 coupled to said first flip-flop 78circuit, said first threshold circuit 34, said second logic invertercircuit 66 and said third logic inverter fiiguit 70 for providing alogic output signal A+B+C+x;

a fourth logic OR binary logic circuit 72 coupled to said secondflip-flop circuit 80, said first logic inverter 58, said second logicinverter 66, said third threshold cirgiit 56 for providing a binarylogic output signal A+B+C+ 1;

circuit means respectively coupling the outputs of said third and fourthOR circuits 60 and 72 respectively to another input S of said second andfirst flip-flop circuits 80 and 78;

a sixth AND binary logic circuit 82 having a first input coupled to theoutput of said third OR logic circuit 60 and a second input coupled tothe output of said fourth OR logic circuit 72; and

a fourth logic inverter circuit 84 coupled to the output of said sixthAND circuit 82 and including circuit means coupling its output toanother input of said second OR circuit 88.

10. The invention as defined by claim 8 and additionally including:

first differentiator means 75 and first diode means D coupled togetherbetween the output of said fifth AND gate 68 and said R input terminalof said first and second flip-flop circuit 78 and 80;

second differentiator means 77 and second diode means D coupled togetherbetween the output of said fourth OR circuit 72 and said S inputterminal of said first flip-flop circuit 78; and

third differentiator means 79 and third diode means D coupled togetherbetween the output of said third OR circuit 60 and said S input of saidsecond flip-flop circuit 80.

11. The invention as defined by claim 6 wherein said binary logiccircuit means includes means for implementing the binary logicexpression:

(A+++x) (A++C+y) A-C+B 1 wherein A is the binary logic output signalfrom said second threshold circuit and A is the complement thereof, B isthe binary logic output signal from said first threshold circuit and P;is the complement thereof,

C is the binary outpt 1t logic signal from said third threshold circuitand C is the complement thereof and 12. The invention as defined byclaim 11 and wherein said logic circuit means is comprised of at least afirst, second and a third logic inverter circuit 58, 66 and coupled tosaid first, second and third threshold circuit 34, 50, and 56 forrespective lyprovidi ng output signals comprising the logic signals A,B, and C.

13. The invention as defined by claim 12 and additionally including:

a first AND binary logic circuit 62 coupled to said first thresholdcircuit 34 and said third threshold circuit 56 for providing a logicoutput signal A-C;

a second AND binary logic circuit 68 having a plurality of inputsrespectively coupled to said first logic inverter 58, said secondthreshold circuit 50 and said third logi c in erter 70 for providing alogic output signal A'B-C;

a first and a second flip-flop circuit 78 and 80 having one inputterminal R coupled to the output of said second AND gate 68 andrespectively providing output signals corresponding to Eand y;

a first OR binary logic circuit 60 coupled to said first flip-flop 78circuit, said first threshold circuit 34, said second logic invertercircuit 66 and said third logic inverter circuit 70 for providing alogic output signal A++O+i;

a second OR binary logic circuit 72 coupled to said second flip-flopcircuit 80, said first logic inverter 58, said second logic inverter 66,said third threshold circuit 56 for providing a binary logic outputsignal A+B+C+y;

circuit means respectively coupling the outputs of said first and secondOR circuits 60 and 72 respectively to another input S of said second andfirst flip-flop circuits 80 and 7 8;

a third AND binary logic circuit 82 having a first input coupled to theoutput of said third OR logic circuit 60 and a second input coupled tothe output of said fourth OR logic circuit 72;

a fourth logic inverter circuit 84 coupled to the output of said thirdAND circuit 82; and

a third OR binary logic circuit 88 having a first input coupled to theoutput of said fourth logic inverter circuit 84, a second input coupledto the output of said first AND circuit 62 and a third input coupled tothe output of said second logic inverter circuit 66, and an outputcoupled to external railway apparatus.

14. The invention as defined by claim 13 and additionally including:

first differentiator means 75 and first diode means D coupled togetherbetween the output of said second AND logic circuit 68 and said oneinput terminal R of said first and second flip-flop circuit 78 andsecond differentiator means 77 and second diode means D coupled togetherbetween the output of said second OR circuit 72 and another input S ofsaid first flip-flop circuit 78; and

third differentiator means 79 and third diode means D coupled togetherbetween the output of said first OR circuit 60 and another input S ofsaid second flip-flop circuit 80.

Q I Page .1 UNITED STATES PATENT OFFICE CERTIFICATE OF CQE CTION PatentNo. 316914370 Dated September 12 1972 lnventofls) 'A-JOY KUMAR PAL 7 Itis certified that error appears in the above-identified patent and thatsaid Letters Patent are hereby corrected as shownv below:

In the heading, the following should appear:

-Assignee: Bortec, Inc. Oak Brook, Illinois-m Disregard the drawingspreceding the specification and claims as well as the view on the coversheet. The specification and claims should be read in conjunction withthe sheets of drawings following the claims, as shown on the attachedsheets.

Signed and sealed this 31st day of December 1974.

(SEAL) Attest:

McCOY M. GIBSON JR. C. MARSHALL DANN Attesting Officer Commissioner ofPatents USCOMM'DC 50376-P69 U.S. GOVERNMENT PRINTlNG OFFICE: I9690-355-33 5 FORM PO-105O (10-69)

1. A system for controlling railway signalling apparatus of the typedescribed, comprising in combination: a section of track including apair of rails adapted to carry electrical current; a first and a secondalternating current shunt coupled across said rails respectively atopposite ends of said track section; an alternating current sourcecoupled across said rails at a location intermediate said shunts; afirst transformer having a primary and a secondary circuit includingcircuit means for coupling the primary circuit thereof across said railsadjacent the location of coupling of said alternating current source; asecond and a third transformer each having a primary and a secondarycircuit and including circuit means coupling the primary circuit inparallel circuit relationship respectively with a segment of a rail onopposite sides of the location of the coupling of said current sourceand said primary circuit of said first transformer, said current sourcefeeding a predetermined magnitude of current in diverse directionsthrough to said rails, said shunts and the primary circuits of saidsecond and third transformer as well as the primary circuit of saidfirst transformer whereupon the travel of a train over said tracksection alters the amount of current flowing in the respective primarycircuits of said three transformers by the shunting action of the wheelsthereof; current rectifier means coupled to the secondary circuits ofsaid first, second, third transformer for providing a DC output signalproportional to the current flow in the respective primary circuits; afirst threshold circuit coupled to said rectifier means coupled to saidsecondary circuit of said first transformer means providing an outputsignal corresponding to a first of two possible binary logic statesduring a first track condition and a second binary logic state when thecurrent in the respective primary decreases to predetermined value inresponse to a second track condition; a second and third thresholdcircuit respectively coupled to the said rectifier means coupled to thesecondary circuits of said second and third transformer, each of saidthreshold circuits providing an output signal corresponding to amutually opposite or second binary logic state during said first trackcondition and a first binary state when the current in the respectivesecondary circuit exceeds a predetermined value in response to saidsecond track condition; and binary logic circuit means coupled to saidfirst, second and third threshold circuits and being responsive to thebinary logic states of the output signals thereof to energize apparatusfor a predetermined binary logic combination of output signals from saidthreshold circuits.
 2. The invention as defined by claim 1 wherein saidalternating current source comprises a constant current, audio frequencytransmitter.
 3. The invention as defined by claim 2 wherein said firstand second shunt circuits are resonant at the frequency of operation ofsaid transmitter thereby providing a relatively low impedance to currentflow between said rails at the location thereof, and additionallyincluding circuit means coupled to the primary circuit of said firsttransformer for tuning said primary circuit to said predeterminedfrequency of said transmitter means so as to be responsive only to acurrent of said predetermined frequency.
 4. The invention as defined byclaim 3 and additionally including circuit means coupled to thesecondary circuits of said second and third transformer for providing alow circuit impedance for a secondary current flow of said predeterminedfrequency while providing a relatively high impedance for all otherfrequencies.
 5. The invention as defined by claim 4 wherein said secondand third transformers comprise current transformers wherein the currentflowing in said secondary circuits is proportional to the current insaid primary circuit and wherein said primary circuits respectivelyprovide a relatively smaller impedance to current flow than said rail.6. The invention as defined by claim 1 wherein said secondary circuit ofsaid second and third transformer each includes a secondary windinghaving a first and a second secondary winding portion; and additionallyincluding a first and second summing transformer, each having a primarywinding and a secondary winding; and including circuit means couplingsaid first secondary winding portion of said second and thirdtransformer in mutually opposite polarity relationship across saidprimary winding of said first summing transformer and said secondsecondary winding portion of said second and third transformer inmutually opposite polarity relationship across said primary winding ofsaid second summing transformer; and circuit means coupling saidsecondary winding of said first summing transformer to said rectifiermeans coupled to said second transformer and means coupling saidsecondary winding of said second summing transformer to said rectifiermeans coupled to said third transformer.
 7. The invention as defined byclaim 6 wherein said second and third transformers are comprised ofcurrent transformers wherein the current flowing in said respectivesecondary windings is proportional to the current in said primarycircuit.
 8. The invention as defined by claim 1 wherein said logiccircuit means includes means for implementing the binary logicexpression: A.C + B.C + A.B.C + A.B.C + (A+B+C+x).(A+B+C+y) 1 wherein Ais the binary logic output signal from said second threshold circuit, Bis the binary logic output signal from said first threshold circuit, Cis the binary output logic signal from said third threshold circuit andwherein x and y are binary logic signals derived by said logic circuitto differentiate the direction of travel of a train over said tracksection, and including a first, second and a third logic invertercircuit coupled to said first, second and third threshold circuit forrespectively providing an output signal comprising the logic signals A,B, and C.
 9. The invention as defined by claim 8 and additionallyincluding a first AND binary logic circuit 76 coupled to the output ofsaid first, second and third logic inverter 58, 66 and 70 for providinga logic output signal A.B.C; a second AND binary logic circuit 62coupled to said first threshold circuit 34 and said third thresholdcircuit 56 for providing a logic output signal A.C; a third AND binarylogic circuit 74 coupled to said third threshold circuit 56 and saidsecond logic inverter circuit 66 for providing a logic output signalB.C; a fourth AND binary logic circuit 64 coupled to said firstthreshold circuit 34 and said second and third logic inverter circuits66 and 70 for providing a logic output signal A.B.C; a first OR binarylogic circuit 86 coupled to the outputs of said first, second and thirdand fourth AND circuits 76, 62, 74 and 64, a second OR circuit 88 havingone input thereof coupled to the output of said first OR circuit 86; afifth AND binary logic circuit 68 having a plurality of inputsrespectively coupled to said first logic inverter 58, said secondthreshold circuit 50 and said third logic inverter 70 for providing alogic output signal A.B.C; a first and a second flip-flop circuit 78 and80 having one input terminal R coupled to the output of said fifth logicAND gate 68 and respectively providing output signals corresponding to xand y; a third OR binary logic circuit 60 coupled to said firstflip-flop 78 circuit, said first threshold circuit 34, said second logicinverter circuit 66 and said third logic inverter circuit 70 forproviding a logic output signal A+B+C+x; a fourth logic OR binary logiccircuit 72 coupled to said second flip-flop circuit 80, said first logicinverter 58, said second logIc inverter 66, said third threshold circuit56 for providing a binary logic output signal A+B+C+y; circuit meansrespectively coupling the outputs of said third and fourth OR circuits60 and 72 respectively to another input S of said second and firstflip-flop circuits 80 and 78; a sixth AND binary logic circuit 82 havinga first input coupled to the output of said third OR logic circuit 60and a second input coupled to the output of said fourth OR logic circuit72; and a fourth logic inverter circuit 84 coupled to the output of saidsixth AND circuit 82 and including circuit means coupling its output toanother input of said second OR circuit
 88. 10. The invention as definedby claim 8 and additionally including: first differentiator means 75 andfirst diode means D3 coupled together between the output of said fifthAND gate 68 and said R input terminal of said first and second flip-flopcircuit 78 and 80; second differentiator means 77 and second diode meansD1 coupled together between the output of said fourth OR circuit 72 andsaid S input terminal of said first flip-flop circuit 78; and thirddifferentiator means 79 and third diode means D2 coupled togetherbetween the output of said third OR circuit 60 and said S input of saidsecond flip-flop circuit
 80. 11. The invention as defined by claim 6wherein said binary logic circuit means includes means for implementingthe binary logic expression: (A+B+C+x) . (A+B+C+y) + A.C+B 1 wherein Ais the binary logic output signal from said second threshold circuit andA is the complement thereof, B is the binary logic output signal fromsaid first threshold circuit and B is the complement thereof, C is thebinary output logic signal from said third threshold circuit and C isthe complement thereof and wherein x and y are binary logic signalsderived by said logic circuit to determine the direction of travel of atrain over said track section.
 12. The invention as defined by claim 11and wherein said logic circuit means is comprised of at least a first,second and a third logic inverter circuit 58, 66 and 70 coupled to saidfirst, second and third threshold circuit 34, 50, and 56 forrespectively providing output signals comprising the logic signals A, B,and C.
 13. The invention as defined by claim 12 and additionallyincluding: a first AND binary logic circuit 62 coupled to said firstthreshold circuit 34 and said third threshold circuit 56 for providing alogic output signal A.C; a second AND binary logic circuit 68 having aplurality of inputs respectively coupled to said first logic inverter58, said second threshold circuit 50 and said third logic inverter 70for providing a logic output signal A.B.C; a first and a secondflip-flop circuit 78 and 80 having one input terminal R coupled to theoutput of said second AND gate 68 and respectively providing outputsignals corresponding to x and y; a first OR binary logic circuit 60coupled to said first flip-flop 78 circuit, said first threshold circuit34, said second logic inverter circuit 66 and said third logic invertercircuit 70 for providing a logic output signal A+B+C+x; a second ORbinary logic circuit 72 coupled to said second flip-flop circuit 80,said first logic inverter 58, said second logic inverter 66, said thirdthreshold circuit 56 for providing a binary logic output signal A+B+C+y;circuit means respectively coupling the outputs of said first and secondOR circuits 60 and 72 respectively to another input S of said second andfirst flip-flop circuits 80 and 78; a third AND binary logic circuit 82having a first input coupled to the output of said third OR logiccircuit 60 and a second input coupled to the output of said fourth ORlogic circuit 72; a fourth logic inverter circuit 84 coupled to theoutput of said third AND circuit 82; and a third OR binary logic circuit88 having a first input coupled to the output of said fourth logicinverter circuit 84, a second input coupled to the output of said firstAND circuit 62 and a third input coupled to the output of said secondlogic inverter circuit 66, and an output coupled to external railwayapparatus.
 14. The invention as defined by claim 13 and additionallyincluding: first differentiator means 75 and first diode means D3coupled together between the output of said second AND logic circuit 68and said one input terminal R of said first and second flip-flop circuit78 and 80; second differentiator means 77 and second diode means D1coupled together between the output of said second OR circuit 72 andanother input S of said first flip-flop circuit 78; and thirddifferentiator means 79 and third diode means D2 coupled togetherbetween the output of said first OR circuit 60 and another input S ofsaid second flip-flop circuit 80.